On May 28, 2026, Huawei and SMIC jointly released a reliability white paper on a front-side copper plating process for planar-gate 1200V SiC MOSFETs. The disclosed results are particularly relevant to power semiconductor design companies, wafer foundry customers, packaging partners, and downstream power electronics manufacturers because they point to measurable changes in short-circuit withstand capability, power cycling performance, and automotive-grade reliability verification.

Event Overview

On May 28, 2026, Huawei and SMIC jointly released the Reliability White Paper on Front-Side Copper Plating Process for Planar-Gate 1200V SiC MOSFETs.

According to the disclosed information, the white paper confirms that an electroplated copper source structure, compared with a traditional AlCu solution, can increase short-circuit withstand time to 2.5 microseconds, representing a 25% improvement. It also extends power cycling life to 500,000 cycles and has passed AEC-Q101 HTRB plus PC 2000-hour accelerated validation.

The disclosed information also states that the technology has entered SMIC's mature foundry platform and can support customized tape-out and volume packaging cooperation for overseas customers.

Which Industry Segments Are Affected

Power Semiconductor Design Companies

Power semiconductor design companies are directly affected because the released white paper concerns a planar-gate 1200V SiC MOSFET process and its reliability performance. For companies developing or evaluating SiC MOSFET products, the key impact lies in whether front-side copper plating can become a process option when balancing short-circuit withstand time, power cycling life, and qualification requirements.

Analysis shows that the disclosed 2.5-microsecond short-circuit withstand time and 500,000-cycle power cycling life may influence how design teams compare metallization schemes, reliability margins, and qualification plans. However, specific product adoption still depends on each company's device design, test conditions, and commercialization schedule.

Wafer Foundry and Process Integration Customers

Foundry customers are affected because the technology has entered SMIC's mature foundry platform. This indicates that the process is no longer only described as a laboratory concept in the disclosed information, but is connected with a foundry platform that supports customized tape-out.

From an industry perspective, companies planning SiC MOSFET tape-out projects may need to pay closer attention to process availability, design rules, reliability data packages, and the boundary between standard platform capability and customer-specific customization. The impact is likely to be most visible in early-stage product definition and foundry engagement.

Packaging and Reliability Validation Partners

Packaging and reliability validation partners may be affected because the disclosed technology involves both front-side copper plating and volume packaging cooperation. The reported AEC-Q101 HTRB plus PC 2000-hour accelerated validation also places reliability testing and packaging coordination at the center of subsequent implementation.

What deserves more attention now is whether packaging flows, interconnection choices, and reliability test plans can align with the characteristics of the electroplated copper source structure. The disclosed information does not provide detailed packaging specifications, so related companies should avoid assuming universal compatibility without project-level verification.

Downstream Power Electronics Manufacturers

Downstream manufacturers that evaluate 1200V SiC MOSFETs are affected because device-level reliability indicators can influence component selection, supplier qualification, and risk assessment. The reported improvement in short-circuit withstand time and power cycling life may become part of future technical discussions between device suppliers and system manufacturers.

It is better understood as a signal for closer technical review rather than an immediate change in procurement standards. Downstream companies should focus on whether future products based on this process can provide complete qualification documents, application-level test results, and stable supply arrangements.

Overseas Customers and Cross-Border Supply Chain Participants

Overseas customers are specifically mentioned in the disclosed information, as the platform supports customized tape-out and volume packaging cooperation for overseas clients. This makes the event relevant to companies seeking foundry and packaging collaboration for SiC MOSFET projects.

Observably, the impact may appear first in technical communication, project feasibility assessment, and sample planning. Companies should still distinguish between platform readiness, customer-specific tape-out progress, and actual mass production delivery for a given product.

Key Points to Watch and Practical Responses

Track Follow-Up Official Disclosures

Companies should continue monitoring official statements from Huawei and SMIC regarding the reliability white paper, the foundry platform, and the scope of customer cooperation. Since the current public information focuses on reliability indicators and platform entry, future disclosures may be important for understanding process boundaries, qualification conditions, and supported product categories.

Review Reliability Requirements Against Project Needs

Design and procurement teams should compare the disclosed short-circuit withstand time of 2.5 microseconds, the 25% improvement over the traditional AlCu scheme, the 500,000-cycle power cycling life, and the AEC-Q101 HTRB plus PC 2000-hour validation against their own product requirements. This review should be conducted as a technical assessment, not as a direct substitute for project-specific validation.

Separate Process Signals from Business Readiness

From an industry perspective, the entry of the technology into a mature foundry platform is an important process signal, but companies should not equate it automatically with immediate availability for every product or market. Before making sourcing or design decisions, firms should clarify tape-out timelines, qualification responsibilities, packaging options, and documentation requirements.

Prepare Early Communication Across Design, Foundry, and Packaging Teams

For companies considering customized tape-out or volume packaging cooperation, early technical communication is more practical than waiting until the procurement stage. Design teams should coordinate with foundry and packaging partners on layout constraints, metallization assumptions, reliability testing plans, and sample evaluation schedules tied to the front-side copper plating process.

Editor’s View / Industry Observation

Analysis shows that this white paper is significant because it links a specific 1200V SiC MOSFET process change with disclosed reliability indicators, including short-circuit withstand time, power cycling life, and accelerated validation under AEC-Q101-related conditions.

It is better understood as both a technical progress signal and a platform-readiness signal. The information indicates that the process has entered SMIC's mature foundry platform and can support overseas customer customization, but the broader market effect will depend on subsequent customer projects, product qualification, and packaging cooperation progress.

What deserves more attention now is not only the improvement over the traditional AlCu solution, but also how related companies verify the process within their own device architectures and commercial requirements. For the industry, the event highlights the growing importance of reliability engineering in SiC MOSFET development.

Conclusion

The joint release by Huawei and SMIC adds a notable reliability-focused development to the 1200V SiC MOSFET supply chain. The disclosed front-side copper plating process shows improved short-circuit withstand capability, longer power cycling life, and accelerated reliability validation results, while also being connected to a mature foundry platform.

From an industry perspective, the news should be viewed rationally as a process and reliability signal with potential implications for design, foundry, packaging, and downstream qualification work. The more suitable response for companies is to track official follow-up information, assess project-level applicability, and prepare technical verification before translating the signal into procurement or product decisions.

Information Sources

Main sources: Huawei and SMIC joint release information on the Reliability White Paper on Front-Side Copper Plating Process for Planar-Gate 1200V SiC MOSFETs, dated May 28, 2026.

Items for continued observation: subsequent official disclosures on platform availability, customer tape-out progress, packaging cooperation details, and product-level qualification outcomes.